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3.15.1. The self-test fails at the memory board icon and reports Error 70 or 71, can it be fixed?

The Lisa's power-on self-test checks the RAM relatively thoroughly. In addition to reporting Error 70 or 71, it also attempts to provide information for repairing memory boards, so yes, repairing a memory board is often possible without a huge effort.

However, before embarking on an effort to repair a memory board, ensure it is truly the memory board that is the problem. A poor connection at the card-edge connector of the CPU board or Memory board can be the cause of errors 70 and 71 (as well as many other error codes). Clean the card-edge connectors (see lisafaq-hw_general_tests.html) and swap around and in/out your memory boards to be sure a particular memory board has a problem.

During the self test, the results of the memory test are stored in some low memory locations (accessible from service mode). Using this information, it is often possible to localize a memory error to a single chip (designated by a row letter and column number), and with some desoldering expertise, the bad chip can be replaced and the memory board repaired.

The low memory locations of the memory test data begin at address $186. There are 16 words of memory bit error information; these 16 words correspond to the sixteen 128K blocks in the 2MB RAM address space.

An examination of the Apple 512K RAM board reveals the memory chips are configured in an array of 4 rows, labelled B,C,D,E and 18 columns (arranged as two groups), labelled 1-9 and 14-22.

Apple 512K memory boards have 4 rows of chips, each row being 128K. This means that 4 of the 16 test result words will exactly correspond to the 4 rows of a single 512K memory board... ie. one word per row.

Each 16 bit word contains bad bit information... a bad data bit is reported by the corresponding bit set to 1 in the word corresponding to the 128K memory block where it was found.


It is easy to associate the bad data bits with the coordinates of a column of 4 chips on the memory board; from the schematic: bit 0 is column 22, bit 7 is column 15, bit 8 is column 1 and bit 15 is column 8.

If there is just one bit set (ie. only one bad chip in a 128K block/row), then there are 16 possible values for the word, which map to memory board columns as follows:

  Word  Bit# = Column
  0001   0   =  22
  0002   1   =  21
  0004   2   =  20
  0008   3   =  19
  0010   4   =  18
  0020   5   =  17
  0040   6   =  16
  0080   7   =  15
  0100   8   =   1
  0200   9   =   2
  0400  10   =   3
  0800  11   =   4
  1000  12   =   5
  2000  13   =   6
  4000  14   =   7
  8000  15   =   8

If there is more than one bad chip in a 128K block, there will be more than one bit set and you'd get a character other than 1,2,4,8, or more than one non-zero character in the word.


The rows of 128K are designated B, C, D, and E by the coordinates on the board. However there is a complication or two...

The 16 words in memory are arranged according to logical address, not physical address, and it is, of course, a physical chip we're looking for. The complication is that the physical rows are mapped to logical addresses in a different order depending on which slot the board is in.

If you have one 512K memory board, regardless of which slot it is in, it will always be associated with the first 4 words... $186 - $18C.

If you have two 512K memory boards, the first 4 words are associated with slot MEM 2, and the next 4 words are associated with slot MEM 1.

The last 8 words are never used with 512K memory boards, since they correspond to the second MB of the logical address space. They would be used if you have more than 1MB of memory.

The four rows of the memory board are always mapped in BCDE or EDCB order (depends on the slot), so you can be confident that a single bit error maps to one of two rows... if the error is in the first or last of four words, then the problem is row B or E. If the error is in the second or third word, then the problem is C or D.

To figure out which of the two rows is the problem, you can read-up on the physical-logical address mapping scheme in the Lisa Hardware Reference Manual, and cross-reference that through the schematic to determine which physical row is going to correspond to which logical address block.

Or you can use a rule of thumb determined by observation...

It has been observed that for slot MEM 1, the order is BCDE, and for slot MEM 2, the order is EDCB.

The rows corresponding to the first 8 words starting at $186 are used as follows:

1 board in slot MEM 1

  B C D E   x x x x

1 board in slot MEM 2
  E D C B   x x x x

2 boards
  MEM 2     MEM 1
  E D C B   B C D E


A. 1 RAM board installed, error reported in first 4 words...

B. Error in second 4 words...

Parity Error 71

You may have noticed something missing... there are 18 columns of chips, not 16. The extra 2 are for parity bits, one for each byte.

If there was a parity error, then all the data bits might be clean, represented by 0 in all 8 words at $186. In this case, you will get error 71 instead of 70 from the memory test.

In the case of a parity error:

  00 = row B when the problem board is in MEM 1, with MEM2 empty
  01 = row C when the problem board is in MEM 1
  02 = row D when the problem board is in MEM 1
  03 = row E when the problem board is in MEM 1

  04 = row B when the problem board is in MEM 1, with 512K in MEM2
  05 = row C when the problem board is in MEM 1
  06 = row D when the problem board is in MEM 1
  07 = row E when the problem board is in MEM 1

  00 = row E when the problem board is in MEM 2, regardless of MEM1
  01 = row D when the problem board is in MEM 2
  02 = row C when the problem board is in MEM 2
  03 = row B when the problem board is in MEM 2


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